The present invention is directed to memory devices and, more particularly, to dynamic random access memory (DRAM) structures formed in a substrate.
Dynamic random access memory devices (DRAMs) typically include a semiconductor memory cell array formed of a plurality of memory cells arranged in rows and columns and include a plurality of bit lines as well as a plurality of word lines that intersect the bit lines. Each memory cell of the array is located at the intersection of a respective word line and a respective bit line and includes a capacitor for storing data and a transistor for switching, such as a planar or vertical MOS transistor. The word line is connected to the gate of the switching transistor, and the bit line is connected to the source or drain of the switching transistor. When the transistor of the memory cell is switched on by a signal on the word line, a data signal is transferred from the capacitor of the memory cell to the bit line connected to the memory cell or from the bit line connected to the memory cell to the capacitor of the memory cell.
When data stored in one of the memory cells is read onto one of the bit lines, for example, a potential difference is generated between the bit line of the respective memory cell and the bit line of another memory cell which form a bit line pair. A bit line sense amplifier connected to the bit line pair senses and amplifies the potential difference and transfers the data from the selected memory cells to a data line pair.
An advantage of DRAMs over other types of memory technology is their low cost because of the simplicity and scaling characteristics of the memory cell. Though the DRAM memory cell is based on simple concepts, the actual design and implementation of such cells typically requires a highly complex DRAM design and process technology.
An example of current DRAM technology is a buried capacitor DRAM memory in which memory bits are constructed in pairs to allow sharing of a bit line contact. The sharing of the bit line contact significantly reduces the overall cell size. Typically, the memory bit pair includes an active area (AA), a pair of word lines, a bit line contact, a metal or polysilicon bit line, and a pair of cell capacitors.
The bit line pitch, i.e., the width of the bit line plus the distance between adjacent bit lines, typically determines the active area pitch and the capacitor pitch. The active area width is typically adjusted to maximize the transistor drive and minimize the transistor-to-transistor leakage.
The word line pitch typically determines the space available for the bit line contact, the transistor length, the active area space, and the capacitor length. Each of these dimensions must be optimized to maximize device capacitance, minimize device leakage and maximize process yield.
A common memory bit is known as an eight square feature or 8F2 cell. By definition, the feature size is the minimum realizable dimension for a given process. In practice, however, the feature size is one-half of the word line (row) pitch or bit line (column) pitch. As an example, a 0.3 μm process having word line and bit line pitches of 0.6 μm typically provides a memory bit size that is 8·(0.3 μm)2=0.72 μm2. The 8F2 designation is best explained by traversing along the outer boundary of a memory cell. Traversing along one axis, the path includes one-half of a bit line contact feature, one word line feature, one capacitor feature, one field polysilicon feature, and one-half of a polysilicon space feature, for a total of 4 feature lengths. Along another axis that is perpendicular thereto, the path includes two one-half field oxide features and one active area feature for a total of two feature lengths. The area of the memory bit is therefore 4F·2F=8F2, also referred to as 8F2.
The folded array architecture always produces an 8F2 memory bit because each word line connects, namely forms a crosspoint, with a memory bit transistor on every other bit line and passes around the memory bit transistors as a field polysilicon layer on the remaining bit lines. The field polysilicon layer in each memory bit cell adds two square features to what otherwise is a 6F2 cell. Though the folded array yields a cell that is 25% larger than the 6F2 array architectures, the folded array results in superior signal-to-noise performance, especially when combined with bit line folding.
As memory devices become increasingly smaller, the width of the deep trench which forms part of the vertical transistor and the capacitor must be made smaller to accommodate the passing word line and the bit line contacts. However, the deep trench cannot be made too small or the trench cannot be filled properly without the presence of voids. As a result, the etch step that forms the deep trench becomes increasingly difficult to control within desired specifications.
Moreover, as these devices become smaller, the trench collar oxide layer that is located along the sidewalls of the deep trenches cannot be formed using existing localized oxidation of silicon (LOCOS) processes and must be formed, instead, by a buried collar or other costly process steps.
Additionally, with such devices, voids may be present in the high-density plasma (HDP) deposited oxide or other dielectrics that are typically used to fill the isolation trenches. Such voids may be present at “triple point” corners where the isolation trench, the silicon substrate and the polysilicon layers meet.
Further, two bit line contacts are typically present for each deep trench, resulting in a significant increase in the bit line capacitance.
It is therefore desirable to provide a DRAM structure and fabrication process that avoids these problems.